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1/17 l9903 october 2005 1 features operating supply voltage 8v to 20v, overvoltage max. 40v operating supply voltage 6v with implemented stepup converter quiescent current in standby mode less than 50a iso 9141 compatible interface charge pump for driving a power mos as reverse battery protection pwm operation frequency up to 30khz programmable cross conduction protection time overvoltage, undervoltage, short circuit and thermal protection real time diagnostic 2 description control circuit for power mos bridge driver in auto- motive applications with iso 9141bus interface. motor bridge controller figure 2. block diagram vs dir pwm en rx tx cp cb1 gh1 s1 gl1 cb2 gh2 s2 gl2 k = pr vcc = = iso-interface vcc gnd st reference bias charge pump control logic overvolt age undervoltage pwm r dir r rx r tx r 0.5 ? v vs r s2 r gl2 r gl1 r s1 r cp r en vcc timer i kh v s2th thermal shutdown v s1th dg vcc r dg v sth f st = - + 10 1 2 4 5 3 6 7 8 20 9 16 15 17 18 19 14 12 13 11 rev. 4 fi gure 1. p ac k age table 1. order codes part number package l9903 so20 L9903TR tape & reel so20
l9903 2/17 table 2. pin function figure 3. pin connection (top view) n pin description 1 st open drain switch for stepup converter 2 dg open drain diagnostic output 3 pwm pwm input for h-bridge control 4 en enable input 5 dir direction select input for h-bridge control 6 pr programmable cross conduction protection time 7 rx iso 9141 interface, receiver output 8 tx iso 9141 interface, transmitter input 9 k iso 9141 interface, bidirectional communication k-line 10 vs supply voltage 11 cp charge pump for driving a power mos as reverse battery protection 12 gh1 gate driver for power mos highside switch in halfbridge 1 13 cb1 external bootstrap capacitor 14 s1 source/drain of halfbridge 1 15 gh2 gate driver for power mos highside switch in halfbridge 2 16 cb2 external bootstrap capacitor 17 s2 source/drain of halfbridge 2 18 gl2 gate driver for power mos lowside switch in halfbridge 2 19 gl1 gate driver for power mos lowside switch in halfbridge 1 20 gnd ground st dg pwm en dir rx pr tx k gh1 cb1 s1 cb2 gh2 s2 gl2 gl1 gnd 1 3 2 4 5 6 7 8 9 18 17 16 15 14 12 13 11 19 10 20 vs cp so20
3/17 l9903 table 3. absolute maximum ratings for externally applied voltages or currents exceedi ng these limits damage of the device may occur! all pins of the ic are protected against esd. the verification is performed according to mil883c, human body model with r=1.5k ? , c=100pf and discharge voltage 2kv, corresponding to a maximum discharge energy of 0.2mj. table 4. thermal data 1. see application note 110 for so packages. . symbol parameter value unit v cb1 , v cb2 bootstrap voltage -0.3 to 40 v i cb1 , i cb2 bootstrap current -100 ma v cp charge pump voltage -0.3 to 40 v i cp charge pump current -1 ma v dir ,v en ,v pwm ,v tx logic input voltage -0.3 to 7 v i dir ,i en ,i pwm ,i tx logic input current 1 ma v dg ,v rx logic output voltage -0.3 to 7 v i dg ,i rx logic output current -1 ma v gh1 , v gh2 gate driver voltage -0.3 to v sx + 10 v i gh1 , i gh2 gate driver current -1 ma v gl1 , v gl2 gate driver voltage -0.3 to 10 v i gl1 , i gl2 gate driver current -10 ma v k k-line voltage -20 to v s v v pr programming input voltage -0.3 to 7 v i pr programming input current -1 ma v s1 , v s2 source/drain voltage -2 to v vs + 2 v i s1 , i s2 source/drain current -10 ma v st output voltage -0.3 to 40 v i st step up output current -1 ma v vsdc dc supply voltage -0.3 to 27 v v vsp pulse supply voltage (t < 500ms) 40 v i vs dc supply current -100 ma symbol parameter value unit t j operating junction temperature -40 to 150 c t jsd junction temperature thermal shutdown threshold min 150 c t jsdh junction thermal shutdown hysteresis typ 15 c r th j-amb thermal resistance junction to ambient 1) 85 c/w
l9903 4/17 table 5. electrical characteristcs (8v < v vs < 20v, v en = high, -40c t j 150c, unless otherwise specified. the voltages are refered to gnd and currents are assumed positive, when current flows into the pin symbol parameter test condition min. typ. max. unit supply (vs) v vs ovh overvoltage disable high threshold 20 22 24 v v vs ovh overvoltage threshold hysteresis 2) 1.6 v v vs uvh undervoltage disable high threshold 67v v vs uvh undervoltage threshold hysteresis 2) 0.66 v i vsl supply current v en = 0 ; v vs = 13.5v; t j < 85c 50 a i vsh supply current, pwm-mode v vs = 13.5v; v en = high; v dir = low; s1 = s2 = gnd f pwm = 20khz; c cbx = 0.1f; c glx = 4.7nf; c ghx = 4.7nf; r pr = 10k ? ; c pr = 150pf 8.1 13 ma i vsd supply current, dc-mode v vs = 13.5v; v en = high; v dir = low; s1 = s2 = gnd v pwm = low; c ghx = 4.7nf r pr = 10k ? ; c pr = 150pf 5.8 10 ma enable input (en) v enl low level 1.5 v v enh high level 3.5 v v enh hysteresis threshold 2) 1v r en input pull down resistance v en = 5v 16 50 100 k ? h-bridge control inputs (dir, pwm) v dirl v pwml input low level 1.5 v v dirh v pwmh input high level 3.5 v v dirh v pwmh input threshold hysteresis 2) 1v r dir r pwm internal pull up resistance to internal vcc 3) v dir = 0; v pwm = 0 16 50 100 k ? diagnostic output (dg) v dg output drop i dg = 1ma 0.6 v r dg internal pull up resistance to internal vcc 3) v dg = 0v 10 20 40 k ? programmable cross conduction protection 4) n pr threshold voltage ratio v prh / v prl r pr = 10k ? 1.822.2 i pr current capability v pr = 2v -0.5 ma iso interface, transmission input (tx) v txl input low level 1.5 v
5/17 l9903 v txh input high level 3.5 v v txh input hysteresis voltage 2) 1 v r tx internal pull up resistance to internal vcc 3) v tx = 0 102040k ? iso interface, receiver output (rx) v rxl output voltage high stage tx = high; i rx = 0; v k = v vs 4.5 5.5 v r rx internal pull up resistance to internal vcc 3) tx = high; v rx = 0v 51020k ? r rxon on resistance to ground tx = low; i rx = 1ma 40 90 ? t rxh output high delay time fig. 1 0.5 s t rxl output low delay time 0.5 s iso interface, k-line (k) v kl input low level -20v 0.45 v vs v kh input high level 0.55 v vs v vs v kh input hysteresis voltage 2) 0.025 v vs 0.8v i kh input current v tx = high -5 25 a r kon on resistance to ground v tx = low; i k =10ma 10 30 ? i ksc short circuit current v tx = low 40 130 ma f k transmission frequency 60 100 khz 2. not tested in production: guaranteed by design and verified in characterization 3. internal v vcc is 4.5v ... 5.5v 4. see page 18 for calculation of programmable cross conduction protection time t kr rise time v vs = 13.5v; fig. 1 external loads at k-line: r k = 510 ? pull up to v vs c k = 2.2nf to gnd 26s t kf fall time 26s t kh switch high delay time 4 17 s t kl switch low delay time 4 17 s t sh short circuit detection time v vs = 13.5v; tx = low v k > 0.55 v vs 10 40 s charge pump v cp charge pump voltage v vs = 8v v vs = 13.5v v vs = 20v v vs +7v v vs +10v v vs +10v v vs +14v v vs +14v v vs +14v table 5. electrical characteristcs (continued) (8v < v vs < 20v, v en = high, -40c t j 150c, unless otherwise specified. the voltages are refered to gnd and currents are assumed positive, when current flows into the pin symbol parameter test condition min. typ. max. unit
l9903 6/17 i cp charging current v cp = v vs + 8v v vs = 13.5v -50 -75 a t cp charging time 2) v cp = v vs + 8v v vs = 13.5v c cp = 10nf 1.2 4 ms f cp charge pump frequency v vs = 13.5v 250 500 750 khz drivers for external highside power mos v cb1 v cb2 bootstrap voltage v vs = 8v; i cbx = 0; v sx = 0 v vs =13.5v; i cbx = 0; v sx = 0 v vs = 20v; i cbx = 0; v sx = 0 7.5 10 10 14 14 14 v v v r gh1l r gh2l on-resistance of sink stage v cbx = 8v; v sx = 0 i ghx = 50ma; t j = 25c 10 ? v cbx = 8v; v sx = 0 i ghx = 50ma; t j = 125c 20 ? r gh1h r gh2h on-resistance of source stage i ghx = -50ma; t j = 25c i ghx = -50ma; t j = 125c 10 20 ? ? v gh1h v gh2h gate on voltage (source) v vs = v sx = 8v; i ghx = 0; c cbx = 0.1f v vs +6.5v v vs +14v v vs = v sx = 13.5v; i ghx = 0; c cbx = 0.1f v vs +10v v vs +14v v vs = v sx = 20v; i ghx = 0; c cbx = 0.1f v vs +10v v vs +14v r gh1 r gh2 gate discharge resistance en = low 10 100 k ? r s1 r s2 sink resistance 10 100 k ? drivers for external lowside power mos r gl1l r gl2l on-resistance of sink stage i glx = 50ma; t j = 25c i glx = 50ma; t j = 125c 10 20 ? ? r gl1h, r gl2h on-resistance of source stage i glx = -50ma; t j = 25c i glx = -50ma; t j = 125c 10 20 ? ? v gl1h, v gl2h gate on voltage (source) v vs = 8v; i glx = 0 v vs = 13.5v; i glx = 0 v vs = 20v; i glx = 0 7v 10v 10v v vs v vs 14v r gl1 r gl2 gate discharge resistance en = low 10 100 k ? 2. not tested in production: guaranteed by design and verified in characterization timing of the drivers t gh1lh t gh2lh propagation delay time fig. 2 v vs = 13.5v v s1 = v s2 =0 c cbx = 0.1f rpr= 10kw 500 ns table 5. electrical characteristcs (continued) (8v < v vs < 20v, v en = high, -40c t j 150c, unless otherwise specified. the voltages are refered to gnd and currents are assumed positive, when current flows into the pin symbol parameter test condition min. typ. max. unit
7/17 l9903 t gh1lh t gh2lh propagation delay time including cross conduction protection time t ccp fig. 2 v vs = 13.5v v s1 = v s2 =0 c cbx = 0.1f c pr = 150pf; r pr = 10k ? ; 5) 0.7 1 1.3 s t gh1hl t gh2hl propagation delay time 500 ns t gl1lh t gl2lh propagation delay time fig. 2 v vs = 13.5v v s1 = v s2 =0 c cbx = 0.1f r pr = 10k ? 500 ns t gl1lh t gl2lh propagation delay time including cross conduction protection time t ccp fig. 2 v vs = 13.5v v s1 = v s2 =0 c cbx = 0.1f c pr = 150pf; r pr = 10k ? ; 5) 0.7 1 1.3 s t gl1hl t gl2hl propagation delay time 500 ns t gh1r t gh2r rise time fig. 2 v vs = 13.5v v s1 = v s2 =0 c cbx = 0.1f c ghx = 4.7nf c glx = 4.7nf r pr = 10k ? ; 1s t gh1f t gh2f fall time 1s t gl1r t gl2r rise time 1s t gl1f t gl2f fall time 1s short circuit detection v s1th v s2th threshold voltage 4 v t scd detection time 5 10 15 s step up converter (st) (5.2v v vs < 10v) v sth st disable high threshold 10 v v sth st disable threshold hysteresis voltage 2) 12v r dson open drain on resistance v vs = 5.2v; i st = 50ma 20 ? f st clock frequency 50 100 149 khz 2. not tested in production: guarante ed by design and verified in characterization 5. tested with differed values in production but guaranteed by design and verified in characterization table 5. electrical characteristcs (continued) (8v < v vs < 20v, v en = high, -40c t j 150c, unless otherwise specified. the voltages are refered to gnd and currents are assumed positive, when current flows into the pin symbol parameter test condition min. typ. max. unit
l9903 8/17 figure 4. timing of the iso-interface figure 5. timing of the drivers for the external mos regarding the inputs dir and pwm t tx v 0.3 ? v vcc 0.7 ? v vcc 0.3 ? v vcc t v k t t kl t kh t kr t kf i k > i ksc 80% 20% 0.55 ? v vs 0.45 ? v vs v rx t rxl t rxh 0.3 ? v vcc 0.7 ? v vcc on off open drain transistor at k-pin t sh 50% t t t 80% 20% t ghxlh t ghxr t ghxf t ghxhl pwm or dir ghx glx t glxhl t glxf t glxlh t glxr 80% 20%
9/17 l9903 figure 6. i(v) characteristics of the k-line for tx = high and vvs=13.5v figure 7. driving sequence -20 -10 0 10 20 vk [v] -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 ik [ma] ~50k ? ~50k ? en dir pwm braking gh1 gl1 gh2 gl2 note: before standby mode (en = low) a braking phase is mandatory to discharge the stored energy of the motor.
l9903 10/17 figure 8. charging time of an external capacitor of 10nf connected to cp pin at v vs =8v and v vs =13.5v figure 9. application circuit diagram 01234 time [ms] 0 5 10 15 20 25 30 voltage [v] charging time of a 10nf load at cp cp for vs=13.5v cp for vs=8v en d1 c gnd k-line c1 r r r r voltage regulator v bat c s2 c s1 r pr c pr c b1 b2 c v cc m vs dir pwm en rx tx cp cb1 gh1 s1 gl1 cb2 gh2 s2 gl2 k = pr vcc = = iso-interface vcc gnd st ref erence bias charge pump control logic overvoltage undervoltage pwm r dir r rx r tx r 0.5 ? v vs r s2 r gl2 r gl1 r s1 r cp r en vcc timer i kh v s2th thermal shutdown v s1th dg vcc r dg v sth f st = - + 10 1 2 4 5 3 6 7 8 20 9 16 15 17 18 19 14 12 13 11
11/17 l9903 3 functional description 3.1 general the l9903 integrated circuit (ic) is designed to control f our external n-channel mos transistors in h-bridge con- figuration for dc-motor driving in automotive applications. it includes an iso9141 compatible interface. a typical application is shown in fig.9. 3.2 voltage supply the ic is supplied via an external reverse battery protection diode to the v vs pin. the typical operating voltage range is down to 8v. the supply current consumption of the ic composes of st atic and a dynamic part. the static current is typically 5.8ma. the dynamical current i dyn is depending of the pwm frequency f pwm and the required gate charge q gate of the external power mos transistor. the current can be estimated by the expression: i dyn = 2 f pwm q gate an external power transistor with a gate charge of q gate = 160nc and a pwm frequency of f pwm = 20khz re- quires a dynamical supply current of i dyn = 6.4ma. the total supply current consumption is i vs = 5.8ma + 6.4ma = 12.2ma. 3.3 extended supply voltage range (st) the operating battery voltage range can be extended down to 6v using the additional components shown in fig.7. a small inductor of l~150h (i peak ~500ma) in series to the battery supply builts up a step up converter with the switching open drain output st. the switching frequency is typical 100khz with a fixed duty cycle of 50%. the step up converter starts below v vs < 8v, increases the supply voltage at the v s pin and switches off at v vs > 10v to avoid eme at nominal battery voltage. the di ode d2 in series with the st pin is necessary only for systems with negative battery voltage. no additional load can be driven by the step up converter. figure 10. v bat l1 d1 d2 c1 c2 vs st v sth f st = - + l9903
l9903 12/17 3.4 control inputs (en, dir, pwm) the cmos level inputs drive the device as shown in fig.7 and described in the truth table. the device is activated with enable input high signal. for enable input floating (not connected) or ven=0v the device is in standby mode. when activating the device a wake-up time of 50s is recommended to stabilize the internal supplies. the dir and pwm inputs control the driv er of the external h-bridge transistors. the motor direction can be choosen with the dir input, the duty cycle and frequency with the pwm input. unconnected inputs are defined by internal pull up resistors. during wake-up and braking and before disactivating the ic via enable both inputs should be driven high. table 6. truth table: symbols: x don't care r:resistive output ts:thermal shutdown 0: logic low or not active l: output in sink condition ov:overvoltage 1: logic high or active h: output in source condition uv:undervoltage t: tristate sc:short circuit 6. only those external mos transistors of the h-bridge which are in short circuit condition are switched off. all others remain driven by dir and pwm. 7. see application note an2229 3.5 thermal shutdown when the junction temperature exceeds t jsd all driver are switched in sink condition (l), the k- output is off and the diagnostic dg is low until the junction temperature drops below t jsd - t jhyst . 3.6 overvoltage shutdown when the supply voltage v vs exceeds the overvoltage threshold v vsovh all driver are switched in sink condition (l), the k- output is off and the diagnostic dg is low. 3.7 undervoltage shutdown for supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (l) and the diagnostic dg is low. status control inputs device status driver stage for external power mos diagnostic comment en dir pwm ts ov uv sc gh1 gl1 gh2 gl2 dg 1 0xxxxxx r 7) r r 7) r t standby mode 2 1xx1000llll l thermal shutdown 3 1xx0100llll l overvoltage 4 1xx0010llll l undervoltage 5 1xx0001 x 6) x 6) x 6) x 6 l short circuit 6) 6 1000000lhhl h 7 1x10000hlhl h braking mode 8 1100000hllh h
13/17 l9903 3.8 short circuit detection the output voltage at the s1 and s2 pin of the h-bridge is m onitored by comparators to detect shorts to ground or battery. the activated external highside mos transistor will be switched off if the voltage drop remains below the comparator threshold voltage v s1th and v s2th for longer than the short current detection time t scd . the transistor remains in off condition, the diagnostic output goes low until the dir or pwm input status will be changed. the status doesn't change for the other mos transis tors. the external lowside mos transistor will be switched off if the voltage drop passes over the comparator threshold voltage v s1th and v s2th for longer than the short current detection time t scd . the transistor remains in off condition, the diagnostic output goes low until the dir or pwm input status will be changed. the status doesn't change for the other mos transistors. 3.9 diagnostic output (dg) the diagnostic output provides a real time error detection, if monitors the following error stacks: thermal shut- down, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. the open drain output with internal pull up resistor is low if an error is occuring. 3.10 bootstrap capacitor (cb1,cb2) to ensure, that the external power mos transistors reach the required r dson , a minimum gate source voltage of 5v for logic level and 10v for standard power mos transistors has to be guaranteed. the highside transistors require a gate voltage higher than the supply voltage. this is achieved with the internal chargepump circuit in combination with the bootstrap capacitor. the bootstrap c apacitor is charged, when the highside mos transistor is off and the lowside is on. when the lowside is switched off, the charged bootstrap capacitor is able to supply the gate driver of the highside power mos transistor. for effective charging the values of the bootstrap capacitors should be larger than the gate-source capac itance of the power mos and respect the required pwm ratio. 3.11 chargepump circuit (cp) the reverse battery protection can be obtained with an exte rnal n-channel mos transistor as shown in fig.6. in this case its drain-bulk diode provides the protection. the output cp is intended to drive the gate of this tran- sistor above the battery voltage to switch on the mos and to bypass the drain-bulk diode with the r dson . the cp has a connection to vs through an internal diode and a 20k ? resistor. 3.12 gate drivers for the external n-channel power mos transistors (gh1, gh2, gl1, gl2) high level at en activates the driver of the external mos under control of the dir and pwm inputs (see truth table and driving sequence fig.4). the external power mos gates are connected via series resistors to the de- vice to reduce electro magnetic emission (eme) of the system. the resistors influence the switching behaviour. they have to be choosen carefully. too large resistors enlarge the charging and discharging time of the power mos gate and can generate cross current in the halfbridges. the driver assures a longer switching delay time from source to sink stage in orde r to prevent the cross conduction. the gate source voltage is limited to 14v. the charge/discharge current is limited by the r dson of the driver. the drivers are not protected against shorts. 3.13 programmable cross conduction protection the external power mos transistors in h-bridge ( two half bridges) configuration are switched on with an addi- tional delay time t ccp to prevent cross conduction in the halfbri dge. the cross conduction protection time t ccp is determined by the external capacitor c pr and resistor r pr at the pr pin. the capacitor c pr is charged up to the voltage limit v prh . a level change on the control inputs dir and pwm switches off the concerned external mos transistor and the charging source at the pr pin. the resistor r pr discharges the capacitor c pr . the con- cerned external power mos transistor will be switched on again when the voltage at pr reaches the value of v prl . after that the cpr will be charged again. the capacitor c pr should be choosen between 100pf and 1nf. the resistor r pr should be higher than 7kw. the delay time can be expressed as follows:
l9903 14/17 t ccp = r pr c pr ln n pr with n pr = v prh / v prl = 2 t ccp = 0.69 r pr c pr 3.14 iso-interface the iso-interface provides the communication between the micro controller and a serial bus with a baud rate up to 60kbit/s via a single wire which is v bat and gnd compatible. the logic level transmission input tx drives the open drain k-output. the k output can be connected to a serial bus with a pull up resistor to v bat . the k- pin is protected against overvoltage, short to gnd and vs and can be driven beyond v vs and gnd. during lack of v vs or gnd the output shows high impedance characteristic. the open drain output rx with an internal pull up resistor monitors the status at the k-pin to read the received data and control the transmitted data. short circuit condition at k-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential at k-pin below the threshold of 0.45v vs . then the rx stays in high condition. a timer starts and switches the open drain transistor after typ. 20s off. a next low at the tx input resets the timer and the open drain transistor switches on again. figure 11. functional schematic of the iso-interface rx tx k v cc r rx 0.5 ? v vs tx r t sh delay = r s q r i kh
15/17 l9903 figure 12. so20 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0? (min.), 8? (max.) ddd 0.10 0.004 (1) ?d? dimension does not include mold flash, protusions or gate burrs. mold flash, protusions or gate burrs shall not exceed 0.15mm per side. so20 0016022 d
l9903 16/17 table 7. revision history date revision description of changes january 2004 3 migration from st-press to edocs dms october 2005 4 inserted on pag 12 an2229 ref.
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 17/17 l9903

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